Authors: Danilo Demarchi, Politecnico di Torino, IT; Ralf Pferdmenges, Infineon Technologies AG, DE; Clement Benoit
Abstract:
This Deliverable reports the discussions and the conclusions taken during the NEREID General Workshop 1, held in Grenoble 12-13 of April 2016, for WP5 “System Design and Heterogeneous Integration”. During this meeting several discussions and round tables have been organized, for stimulating the interaction among the participants, linking industrial and academic partners. In particular, related to WP5, most of the work has been focused on choosing the best approach for the preparation of the Roadmap. In fact, System Design and Heterogeneous Integration are two topics very difficult to insert in a specific grid, due to their intrinsic multidisciplinarity and broad range of topics. For example, in System Design must be taken in account the four different description levels (physical, device, architectural, system) for obtaining the correct description of the system and its related models. For these reasons the conclusions reached after the Workshop interactions are that it is impossible to categorize and numerically measure the Figure of Merits in System Design roadmap, but a similar approach as the one used in System Design has to be applied: in a first step the System Design and Heterogeneous Integration Roadmap must be built with a top-down approach, starting from the application of reference, remembering that in this domain the right approach has to be Application-Driven. Then, individuated the tree description of the design roadmap, this has to be filled with a bottom-up process, where the detailed specifications and requests are indicated.
Publication Date: 2016/08/07
Location of Publication: NEREID website
Keywords: Semiconductors; Analogue/Mixed Signal Design; Hardware Physical Design; Research/Education
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